FPGA Test Time Reduction Through a Novel Interconnect Testing Scheme

As device densities increase, testing cost is becoming a larger portion of the overall FPGA manufacturing cost. We present an approach to speed up testing FPGA interconnect by reconfiguring it during the test. Simple additions are made to create feedback shift register structures, which considerably reduce the number of test configurations for the switching matrix interconnect. This new testing architecture reduces switching matrix test time by 66 % and the diagnosis time by 72%. The additions are transparent to the users both in terms of speed and functionality