Add to ORKGIn this paper, we present a layer assignment method for high-performance multi-chip module environments. In contrast with treating global routing and layer assignment separately, our method assigns nets to layers while considering preferable global routing topologies simultaneously. We take transmission line effects into account to avoid noise in high-speed circuit packages. The problem is formulated as a quadratic Boolean programming problem and an algorithm is presented to solve the problem after linearization. Our method is applied to a set of benchmark circuits to demonstrate the effectiveness.
Channel routing is a key problem in VLSI physical design. The main goal of the channel routing probl...
In this thesis algorithms for solving performance-driven chip floorplanning and global routing probl...
This paper addresses a delay-driven layer assignment problem with consideration of via delay and cou...
In this paper, we present a layer assignment method for high-performance multi-chip module environme...
[[abstract]]Antenna effect is an important issue that needs to be considered in the routing stage fo...
Aim of this paper is to describe a multi-layer grid routing algorithm which gives a better result ov...
We present a pin-assignment algorithm based on a new multi-layer chip-level global router. Combining...
172 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1993.This thesis deals with four p...
In this thesis, we solve several important routing problems in the physical design of VLSI circuits....
As technology advances, the effect of intra-module delays become less significant, while the effect ...
Given a multilayer routing area, we consider the global routing problem of selecting a maximum set o...
© 2015 IEEE. As the very large scale integration (VLSI) technology enters the nanoscale regime, VLSI...
[[abstract]]Given the geometry of wires for interconnections, the authors want to assign two conduct...
The routing environment for the new emerging mixed-signal System-on-Package (SOP) technology is more...
A channel is a rectangular area of a VLSI (Very Large Scale Integrated) chip which is used to make e...
Channel routing is a key problem in VLSI physical design. The main goal of the channel routing probl...
In this thesis algorithms for solving performance-driven chip floorplanning and global routing probl...
This paper addresses a delay-driven layer assignment problem with consideration of via delay and cou...
In this paper, we present a layer assignment method for high-performance multi-chip module environme...
[[abstract]]Antenna effect is an important issue that needs to be considered in the routing stage fo...
Aim of this paper is to describe a multi-layer grid routing algorithm which gives a better result ov...
We present a pin-assignment algorithm based on a new multi-layer chip-level global router. Combining...
172 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1993.This thesis deals with four p...
In this thesis, we solve several important routing problems in the physical design of VLSI circuits....
As technology advances, the effect of intra-module delays become less significant, while the effect ...
Given a multilayer routing area, we consider the global routing problem of selecting a maximum set o...
© 2015 IEEE. As the very large scale integration (VLSI) technology enters the nanoscale regime, VLSI...
[[abstract]]Given the geometry of wires for interconnections, the authors want to assign two conduct...
The routing environment for the new emerging mixed-signal System-on-Package (SOP) technology is more...
A channel is a rectangular area of a VLSI (Very Large Scale Integrated) chip which is used to make e...
Channel routing is a key problem in VLSI physical design. The main goal of the channel routing probl...
In this thesis algorithms for solving performance-driven chip floorplanning and global routing probl...
This paper addresses a delay-driven layer assignment problem with consideration of via delay and cou...