Sohini Dasgupta, Alex Yakovlev: Modeling and Performance Analysis of GALS Architectures Modeling and Performance Analysis of GALS Architectures

Due to the increase in complexity of distributing a global clock over a single die globally asyn-chronous and locally synchronous systems are becoming an efficient alternative technique to design distributed SoCs. Number of independently clocked synchronous domains can be integrated by clock pausing, clock stretching or data driven clock techniques. Such techniques are applied on point-to-point inter-domain communication schemes. We present here a comparison of these schemes and how it can be applied to an exisiting partitioned synchronous architecture to obtain a reliable, low latency and efficient clock control architectures. The comparison highlights the advantages and disadvantages of one scheme over the other in terms of logical correctness, circuit implementation, performance and relative power consumption. We also present here circuit solutions for stretchable and data driven clocking schemes. These circuit solutions can be easily plugged into existing partitioned synchronous islands. To enable early evaluation of functional correct-ness, this paper proposes the use of Petri net modeling technique to model the asynchronous control blocks that constitute the interface between the synchronous islands.