A probabilistic power estimation technique for combinational circuits is presented. A novel set of simple waveforms is the kernel of this technique. The transition density of each circuit node is estimated. Existing methods have local glitch filtering approaches that fail to model this phenomenon correctly. Glitches originated from a node may be filtered in some, but not necessarily all, of its successor nodes. Our waveform set approach allows us to utilize a global glitch filtering technique that can model the removal of glitches in more detail. It produces error free estimates for tree structured circuits. For other circuit, experimental results using the ISCAS’85 benchmarks show that the waveform set method generally provides significant...
In combinational logic circuits, a single switching event on the primary inputs may give rise to mul...
With the advent of portable and high-density microelectronic devices � the power dissipation of very...
We present techniques for estimating switching activity and power consumption in register-transfer l...
We present a new method of gate-level power estimation that combines the advantages of simulation-ba...
Power disspiation is a growing concern in VLSI circuits. In this work we model the data dependence o...
Our aim is the development of a novel probabilistic method to estimate the power consumption of a co...
Power dissipation in a VLSI circuit poses a serious challenge in present and future VLSI design. A s...
As mobile and portable information systems are becoming more popular, there is a need for the develo...
A power estimation approach is presented in which blocks of consecutive vectors are selected at rand...
Abstract – A power estimation approach is presented in which blocks of consecutive vectors are selec...
Recently developed methods for power estimation have primarily focused on combinational logic, We pr...
In this paper an enhanced gate-level power estimation tool with efficient glitch modeling is present...
In [2] Savir, Ditlow, and Bardell presented an algorithm for estimating the signal probability of a ...
The trend in the integrated circuit industry towards an ever greater miniaturization of circuit comp...
In CMOS circuits, glitches account for a sizable part of the total power consumption. In this paper,...
In combinational logic circuits, a single switching event on the primary inputs may give rise to mul...
With the advent of portable and high-density microelectronic devices � the power dissipation of very...
We present techniques for estimating switching activity and power consumption in register-transfer l...
We present a new method of gate-level power estimation that combines the advantages of simulation-ba...
Power disspiation is a growing concern in VLSI circuits. In this work we model the data dependence o...
Our aim is the development of a novel probabilistic method to estimate the power consumption of a co...
Power dissipation in a VLSI circuit poses a serious challenge in present and future VLSI design. A s...
As mobile and portable information systems are becoming more popular, there is a need for the develo...
A power estimation approach is presented in which blocks of consecutive vectors are selected at rand...
Abstract – A power estimation approach is presented in which blocks of consecutive vectors are selec...
Recently developed methods for power estimation have primarily focused on combinational logic, We pr...
In this paper an enhanced gate-level power estimation tool with efficient glitch modeling is present...
In [2] Savir, Ditlow, and Bardell presented an algorithm for estimating the signal probability of a ...
The trend in the integrated circuit industry towards an ever greater miniaturization of circuit comp...
In CMOS circuits, glitches account for a sizable part of the total power consumption. In this paper,...
In combinational logic circuits, a single switching event on the primary inputs may give rise to mul...
With the advent of portable and high-density microelectronic devices � the power dissipation of very...
We present techniques for estimating switching activity and power consumption in register-transfer l...