A Simulation-Based Methodology for SRAM Defect Analysis and Diagnosis

We propose a methodology for systematically injecting defects into an SRAM and simulating the effects. The detectto-fault mapping tables can be constructed after the simulation. With such tables, memory diagnosis for design debugging and yield improvement can be done more efficiently. The analysis of the circuit defects helps the memory designers and process engineers locate the weakness of the memory chips. The defect and fault detectability obtained from the analysis also can be used for optimizing the test algorithm and the redundancy structure of the memory. Experimental results show that using a March 17N algorithm for a typical SRAM design, we found only 2.47 % of the defects that have escaped the test. 1