An MDE Approach for Implementing Partial Dynamic Reconfiguration in FPGAs

Field programmable gate arrays (FPGAs) provide an interesting solution when custom logic is needed for short time to market products. The products embedding FPGA System on chip solutions allow them to be updated once deployed. Recent FPGA architectures, such as Xilinx Virtex Series, allow for partial and dynamic run-time reconfiguration (PDR). The FPGA fabric can modify its configuration data at run-time, enabling substitution of specific portions of an implemented hardware design causing the system to be adapted to the needs of the application. Hence reliability, failure-redundancy and run-time adaptivity by usage of PDR are introduced that are critical aspects for embedded systems. In this paper, we present a work in progress to provide high level modeling of PDR and a design flow to automatically generate VHDL code from these high level models depending on QoS criteria such as reconfiguration time, performance and power consumption