PARITY ERROR DETECTION IN EMBEDDED SYSTEM

Abstract: In this article we describe one suitable approach that enables the designer to insert a boundary-scan and built-in-self-test concepts, as typical designfor-testability techniques in system-on-chip and multichip module embedded system design, for fault-effects detection. For transient error detection implementation of parity error detection into a 36-bit bus transceiver circuit (32-bit data & four parity bits) is given. The bus transceiver can be implemented as custom or semi-custom integrated circuit in submicron technology and low cost FPGA or CPLD circuit, core within a system-on-a-chip, or glue logic (bridge) within the multichip module