Abstract- In this paper, two issues about wire width are investigated. The first one is that “Is the minimum wire width under the minimum wire pitch for a process technology good enough from the perspective of timing performance? ” The second is that “Is delay sensitive to wire width variation around the optimal width? ” We find that the answer to the first issue is “yes”, whereas the answer to the second is “not quite”. Based on the later property, wire width/spacing can be sized to reduce shorts or opens on interconnects so that manufacturing yield can be improved without hampering too much performance. I
The problem of sizing gates for power-delay tradeos is of great interest to designers. In this work,...
This paper proposes Wire Sizing considering skin effect. Previous work on Wire Sizing usually uses R...
Abstract: This paper considers the problem of interconnect wire delay in digital integrated circuits...
In this paper, we consider non-uniform wire-sizing. Given a wire segment of length L, let f(x) be th...
As the VLSI feature size has already decreased below lithographic wavelength, the printability probl...
We present ecient, optimal algorithms for tim-ing optimization by discrete wire sizing and buer in-s...
In this paper, we study the simultaneous driver and wire sizing (SDWS) problem under two objective f...
In this paper, we develop a set of delay estimation models with consideration of various interconnec...
Abstract—In this paper, we propose a statistical gate sizing ap-proach to maximize the timing yield ...
An e#cient solution to the wire sizing problem #WSP# using the Elmore delay model is proposed. Two f...
This lecture covers the impact of technology scaling on wire delay, and how this affects memory acce...
Based on idealized interconnect scaling rules, we derive the optimal distribution of linewidths as a...
Concern about the performance of wires in scaled technologies has led to research exploring other co...
Conventional methods for optimal sizing of wires and transistors use linear RC circuit models and th...
This paper presents a unique approach to improve yield given a routed layout. Currently after routin...
The problem of sizing gates for power-delay tradeos is of great interest to designers. In this work,...
This paper proposes Wire Sizing considering skin effect. Previous work on Wire Sizing usually uses R...
Abstract: This paper considers the problem of interconnect wire delay in digital integrated circuits...
In this paper, we consider non-uniform wire-sizing. Given a wire segment of length L, let f(x) be th...
As the VLSI feature size has already decreased below lithographic wavelength, the printability probl...
We present ecient, optimal algorithms for tim-ing optimization by discrete wire sizing and buer in-s...
In this paper, we study the simultaneous driver and wire sizing (SDWS) problem under two objective f...
In this paper, we develop a set of delay estimation models with consideration of various interconnec...
Abstract—In this paper, we propose a statistical gate sizing ap-proach to maximize the timing yield ...
An e#cient solution to the wire sizing problem #WSP# using the Elmore delay model is proposed. Two f...
This lecture covers the impact of technology scaling on wire delay, and how this affects memory acce...
Based on idealized interconnect scaling rules, we derive the optimal distribution of linewidths as a...
Concern about the performance of wires in scaled technologies has led to research exploring other co...
Conventional methods for optimal sizing of wires and transistors use linear RC circuit models and th...
This paper presents a unique approach to improve yield given a routed layout. Currently after routin...
The problem of sizing gates for power-delay tradeos is of great interest to designers. In this work,...
This paper proposes Wire Sizing considering skin effect. Previous work on Wire Sizing usually uses R...
Abstract: This paper considers the problem of interconnect wire delay in digital integrated circuits...