In this paper we present a genetic approach for the efficient generation of an encoder to minimize switching activity on the high-capacity lines of a communication bus. The approach is a static one in the sense that the encoder is realized ad hoc according to the traffic on the bus. This is not, however, a limiting hypothesis if the application scenario considered is that of embedded systems. An embedded system, in fact, executes the same application throughout its lifetime and so it is possible to have detailed knowledge of the trace of the patterns transmitted on a bus following execution of a specific application. The approach is compared with the most efficient encoding schemes proposed in the literature on both multiplexed and separate...
Copyright © 2017 American Scientific Publishers. All rights reserved. Energy, delay and noise immuni...
This paper presents two bus coding schemes for power optimization of application-specific systems: ...
Compression of executable code in embedded microprocessor systems, used in the past mainly to reduce...
The power dissipated by system-level buses is the largest contribution to the global power of comple...
The power dissipated by system-level buses is the largest contribution to the global power of compl...
In microprocessor-based systems, large power savings can be achieved through reduction of the transi...
Abstract — This paper presents a solution to the problem of reducing the power dissipated by a digit...
We explore the possibility of reducing energy consumed by on-chip buses via stateful and stateless c...
The energy consumption at the I/O pins is a significant part of the overall chip consumption. This p...
We present a partial bus-invert coding scheme for power optimization of system level bus. In the pro...
In this paper we present algorithms for the synthesis of encoding and decoding interface logic that...
With the rapid increase in the complexity of chips and the popularity of portable devices, the perfo...
A data-distribution and bus-structure aware methodology for the design of coding schemes for low-pow...
Transitions on high capacitance busses in VLSI systems result in considerable power dissipation. Var...
Copyright © 2017 American Scientific Publishers. All rights reserved. Energy, delay and noise immuni...
This paper presents two bus coding schemes for power optimization of application-specific systems: ...
Compression of executable code in embedded microprocessor systems, used in the past mainly to reduce...
The power dissipated by system-level buses is the largest contribution to the global power of comple...
The power dissipated by system-level buses is the largest contribution to the global power of compl...
In microprocessor-based systems, large power savings can be achieved through reduction of the transi...
Abstract — This paper presents a solution to the problem of reducing the power dissipated by a digit...
We explore the possibility of reducing energy consumed by on-chip buses via stateful and stateless c...
The energy consumption at the I/O pins is a significant part of the overall chip consumption. This p...
We present a partial bus-invert coding scheme for power optimization of system level bus. In the pro...
In this paper we present algorithms for the synthesis of encoding and decoding interface logic that...
With the rapid increase in the complexity of chips and the popularity of portable devices, the perfo...
A data-distribution and bus-structure aware methodology for the design of coding schemes for low-pow...
Transitions on high capacitance busses in VLSI systems result in considerable power dissipation. Var...
Copyright © 2017 American Scientific Publishers. All rights reserved. Energy, delay and noise immuni...
This paper presents two bus coding schemes for power optimization of application-specific systems: ...
Compression of executable code in embedded microprocessor systems, used in the past mainly to reduce...