Lecture Overview

This lecture covers the impact of technology scaling on wire delay, and how this affects memory access time and the overall architecture of the system. Fabrication Scaling As learned in the last lecture, each generation of fabrication scaling results in a 30 % reduction in the minimum transistor dimensions. Because of this, wire dimensions must also scale downwards by 30 % in order to fit the sizing of the transistors that they connect to in a circuit. Transistor speeds are increasing linearly with decreasing gate length, and therefore gate delay is decreasing linearly as well. Unfortunately, with decreasing wire height and width (for a fixed length of wire), the delay through wires is actually increasing. Since gate delay is decreasing and wire delay is increasing, a growing gap between the two is emerging, somewhere between quadratic and cubic (1). Wire delays are now becoming a major factor of design consideration in circuits. Back in 1985-1990, wire delays were considered irrelevant to the overall performance of a circuit since the technology then allowed much larger wires that produced faster speeds. In 2002, many technology generations later, the wire delay is so significant in circuit performance that the Pentium 4 used 3 of its 20 pipeline stages just for propagating the signal through the wires! This problem will only worsen in the future as scaling is continued more rigorously