This paper presents and studies a distributed L2 cache management approach through OS-level page allocation for future many-core processors. L2 cache management is a crucial multicore processor design aspect to overcome non-uniform cache access latency for good program performance and to reduce on-chip network traffic and related power consumption. Unlike previously studied hardwarebased private and shared cache designs implementing a “fixed ” caching policy, the proposed OS-microarchitecture approach is flexible; it can easily implement a wide spectrum of L2 caching policies without complex hardware support. Furthermore, our approach can provide differentiated execution environment to running programs by dynamically controlling data placem...
The role of the operating system (OS) in managing shared resources such as CPU time, memory, periphe...
Contention for shared cache resources has been recognized as a major bottleneck for multicores—espec...
Many modern multi-core processors sport a large shared cache with the primary goal of enhancing the ...
Abstract—Most of today’s multi-core processors feature shared L2 caches. A major problem faced by su...
Journal ArticleIn future multi-cores, large amounts of delay and power will be spent accessing data...
On-chip L2 cache architectures, well established in high-performance parallel computing systems, are...
Our thesis is that operating systems should manage the on-chip shared caches of multicore processors...
This thesis proposes a software-oriented distributed shared cache management approach for chip multi...
Shared last level cache has been widely used in modern multicore processors. However, uncontrolled c...
Chip multiprocessors (CMPs) are becoming a popular way of exploiting ever-increasing number of on-ch...
Abstract—Many modern multi-core processors sport a large shared cache with the primary goal of enhan...
The cost of a cache miss depends heavily on the location of the main memory that backs the missing l...
The cost of exploiting the remaining instruction-level par-allelism (ILP) in the applications has mo...
Multi-core processors seek for a large last level cache to enhance the overall performance of the sy...
The design of the memory hierarchy in a multi-core architecture is a critical component since it mus...
The role of the operating system (OS) in managing shared resources such as CPU time, memory, periphe...
Contention for shared cache resources has been recognized as a major bottleneck for multicores—espec...
Many modern multi-core processors sport a large shared cache with the primary goal of enhancing the ...
Abstract—Most of today’s multi-core processors feature shared L2 caches. A major problem faced by su...
Journal ArticleIn future multi-cores, large amounts of delay and power will be spent accessing data...
On-chip L2 cache architectures, well established in high-performance parallel computing systems, are...
Our thesis is that operating systems should manage the on-chip shared caches of multicore processors...
This thesis proposes a software-oriented distributed shared cache management approach for chip multi...
Shared last level cache has been widely used in modern multicore processors. However, uncontrolled c...
Chip multiprocessors (CMPs) are becoming a popular way of exploiting ever-increasing number of on-ch...
Abstract—Many modern multi-core processors sport a large shared cache with the primary goal of enhan...
The cost of a cache miss depends heavily on the location of the main memory that backs the missing l...
The cost of exploiting the remaining instruction-level par-allelism (ILP) in the applications has mo...
Multi-core processors seek for a large last level cache to enhance the overall performance of the sy...
The design of the memory hierarchy in a multi-core architecture is a critical component since it mus...
The role of the operating system (OS) in managing shared resources such as CPU time, memory, periphe...
Contention for shared cache resources has been recognized as a major bottleneck for multicores—espec...
Many modern multi-core processors sport a large shared cache with the primary goal of enhancing the ...