Managing the complexity of performance monitoring hardware: The brink and abyss approach

Recent microprocessor advances have significantly improved the capabilities of on-chip performance monitoring hardware, as is evident in the Pentium 4 processor (Sprunt 2002a). However, the complexity of the performance monitoring hardware has also risen, making the tasks of understanding and using the performance monitoring hardware much more difficult for performance analysts and software developers. Additionally, documentation for these features is becoming increasingly cryptic (Intel Corporation a), further exacerbating the task of using these features effectively. This paper describes a new approach for managing this complexity that enables the full feature set of this hardware to be used while still providing a highlevel, easy-to-use interface. This approach augments referenc