The following buffer management problem arises in network switches providing differentiated services: At the beginning of each time step, one packet can be sent, and afterwards an arbitrary number of new packets arrive. Packets that are not sent can be stored in a buffer. Each packet is attributed by a deadline, and a packet is automatically deleted from the buffer if it is still stored in the buffer by the end of its deadline. The differentiated service model is abstracted by attributing each packet with a value according to its service level. A buffer management strategy determines the packet to be sent in each time step. The goal of a buffer management strategy is to maximize the sum of the values of sent packets. We introduce the concep...
This paper addresses scheduling and memory management in input queued switches with finite input buf...
One of the main problems concerning high-performance communications networks is the unavoidable cong...
Switch and router architectures employing a shared buffer are known to provide high throughput, low ...
We consider the following buffer management problem arising in QoS networks: packets with specified ...
Abstract. We consider FIFO buffer management for switches providing differentiated services. In each...
We consider FIFO buffer management for switches providing differentiated services. In each time step...
textabstractWe consider a network providing Differentiated Services (Diffserv), which allow Internet...
We consider the following buffer management problem arising in QoS networks: packets with specified ...
In this work, we study the problem of buffer management in network switches from an algorithmic pers...
In this paper a special kind of buffer management policy is studied where the packet are preempted e...
The following online problem arises in network devices, e.g., switches, with quality of service (QoS...
We study the behavior of algorithms for buffering packets weighted by different levels of Quality of...
The following online problem arises in network devices, e.g., switches, with quality of service (QoS...
We study the utility of buffer at switches in increasing the achievable utilization of a network pro...
Abstract. In the problem of buffer management with bounded delay, packets with weights and deadlines...
This paper addresses scheduling and memory management in input queued switches with finite input buf...
One of the main problems concerning high-performance communications networks is the unavoidable cong...
Switch and router architectures employing a shared buffer are known to provide high throughput, low ...
We consider the following buffer management problem arising in QoS networks: packets with specified ...
Abstract. We consider FIFO buffer management for switches providing differentiated services. In each...
We consider FIFO buffer management for switches providing differentiated services. In each time step...
textabstractWe consider a network providing Differentiated Services (Diffserv), which allow Internet...
We consider the following buffer management problem arising in QoS networks: packets with specified ...
In this work, we study the problem of buffer management in network switches from an algorithmic pers...
In this paper a special kind of buffer management policy is studied where the packet are preempted e...
The following online problem arises in network devices, e.g., switches, with quality of service (QoS...
We study the behavior of algorithms for buffering packets weighted by different levels of Quality of...
The following online problem arises in network devices, e.g., switches, with quality of service (QoS...
We study the utility of buffer at switches in increasing the achievable utilization of a network pro...
Abstract. In the problem of buffer management with bounded delay, packets with weights and deadlines...
This paper addresses scheduling and memory management in input queued switches with finite input buf...
One of the main problems concerning high-performance communications networks is the unavoidable cong...
Switch and router architectures employing a shared buffer are known to provide high throughput, low ...