Kestrel: Design of an 8-bit SIMD parallel processor

Kestrel is a high-performance programmable parallel co-processor. Its design is the result of examination and reexamination of algorithmic, architectural, packaging, and silicon design issues, and the interrelations between them. The nal system features a linear array of 8-bit processing elements, each with local memory, an arithmetic logic unit (ALU), a multiplier, and other functional units. Sixty-four Kestrel processing elements t in a 1.4 million transistor, 60 mm 2, 0.5 m CMOS chip with just 84 pins. The planned single-board, 8-chip system will, for some applications, provide supercomputer performance atafraction of the cost. This paper surveys four of our applications (sequence analysis, neural networks, image compression, and oating-point arithmetic), and discusses the philosophy behind many of the design decisions. We present the processing element and system architectures, emphasizing the ALU and comparator's compact instruction encoding and design, the architecture's facility with nested conditionals, and the multiplier's exibility in performing multiprecision operations. Finally, we discuss the implementation and performance of the Kestrel test chips.