Analysis of Subthreshold Leakage Reduction in CMOS Digital Circuits

Abstract — Leakage power dissipation has become a sizable proportion of the total power dissipation in an integrated circuit and is projected to grow exponentially during the next decade according to the International Technology Roadmap for Semiconductors (ITRS). This directly affects portable battery operated devices such as cellular phones and PDAs since they have long idle times. To curtail this static power loss, several techniques have been proposed that efficiently minimize leakage power dissipation. A comprehensive survey and analysis of various subthreshold leakage power reduction techniques that are applicable to current battery operated devices is presented in this work. Of particular interest are static CMOS circuits. First, various leakage control techniques applicable to portable devices are briefly described. Specific design constraints for each technique are also enumerated along with some mathematical analysis. Following this, the experimental setup for a comprehensive and fair analysis is described. Circuit parameters such as dynamic (switching) power, leakage power and propagation delay form the basis for the evaluation. A 1-bit full adder is first implemented and characterized for the aforementioned performance metrics. There after, the surveyed techniques are implemented over this full adder and evaluated with the same performance metrics. The results of the analysis are then presented that clearly show a tradeoff between leakage power and other circuit performance parameters. Based on this analysis, a designer or an automation tool would be able to select the appropriate leakage control technique for a particular application