The Effect of the System Specification on the Optimal Selection of Clocked Storage Elements

Abstract—This paper represents a departure from the conventional methods of design and analysis of clocked storage elements that rely on minimizing a fixed energy–delay metric. Instead it establishes a systematic comparison in the energy–delay design space based on the parameters of the surrounding blocks. We define the composite energy-efficient characteristic over all storage element topologies and identify the most efficient storage element depending on its position on the composite characteristic relative to other topologies within a pipeline stage. Thus, we show that an optimal design could use a mixed variety of clocked storage elements (CSEs) depending on their placement in the pipeline and critical path. Since a well-designed system has hardware intensities balanced for a given cycle, a CSE choice will be made depending on the pipeline and path intensities. We show that a meaningful comparison can be carried out only by acknowledging that the optimal design and choice of the clocked storage elements depends heavily on the application, and by analyzing the energy and delay of the clocked storage elements in context of this application. The analysis in the energy–delay space allows us to understand some intuitive design choices in a quantitative way and to identify the optimal storage element topologies for an arbitrary system specification. Index Terms—Clocked storage elements, energy delay optimization, flip-flops, VLSI, power consumption, registers, circuit tuning, circuit optimization, delay effects, circuit analysis, integrated circuit design, CMOS digital integrated circuits, energy measurement