Add to ORKGmethodology is proposed for subthreshold leakage power reduction in nanometer FPGAs. The methodology uses the circuit timing information to tune the performance penalty due to sleep transistors according to the path delays, achieving an average leakage reduction of 44.36 % when applied to FPGA benchmarks using a CMOS 0.13µm process. Moreover, the methodology is applied to several FPGA architectures and CMOS technologies. I
With the growing scaling of technology, leakage power dissipation has become a critical issue of VLS...
With the advent of deep-submicron technologies, leakage power dissipation is a major concern for sca...
nevertheless the leakage currents are leftover as an adverse effect. The problem has taken a serious...
The scaling of the CMOS technology has precipitated an exponential increase in both subthreshold and...
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer...
High leakage current in deep sub-micron regimes is a significant contributor to the power dissipatio...
In the sub-65 nm CMOS technologies, subthreshold and gate dielectric leakage currents need to be sim...
Minimizations of power dissipation, chip area with higher circuit performance are the necessary and ...
Transistor leakage is poised to become the dominant source of power dissipation in digital systems, ...
This paper introduces a new approach to sub-threshold leakage power reduction in CMOS circuits. Our ...
As technology scales down and CMOS circuits are powered by lower supply voltages, standby leakage cu...
Minimizing dynamic power consumption in digital circuits was the primary design objective in most of...
In this paper, two packing algorithms for the detection of ac-tivity profiles in MTCMOS-based FPGA s...
CMOS technology has scaled aggressively over the past few decades in an effort to enhance functional...
Abstract — Leakage power dissipation has become a sizable proportion of the total power dissipation ...
With the growing scaling of technology, leakage power dissipation has become a critical issue of VLS...
With the advent of deep-submicron technologies, leakage power dissipation is a major concern for sca...
nevertheless the leakage currents are leftover as an adverse effect. The problem has taken a serious...
The scaling of the CMOS technology has precipitated an exponential increase in both subthreshold and...
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer...
High leakage current in deep sub-micron regimes is a significant contributor to the power dissipatio...
In the sub-65 nm CMOS technologies, subthreshold and gate dielectric leakage currents need to be sim...
Minimizations of power dissipation, chip area with higher circuit performance are the necessary and ...
Transistor leakage is poised to become the dominant source of power dissipation in digital systems, ...
This paper introduces a new approach to sub-threshold leakage power reduction in CMOS circuits. Our ...
As technology scales down and CMOS circuits are powered by lower supply voltages, standby leakage cu...
Minimizing dynamic power consumption in digital circuits was the primary design objective in most of...
In this paper, two packing algorithms for the detection of ac-tivity profiles in MTCMOS-based FPGA s...
CMOS technology has scaled aggressively over the past few decades in an effort to enhance functional...
Abstract — Leakage power dissipation has become a sizable proportion of the total power dissipation ...
With the growing scaling of technology, leakage power dissipation has become a critical issue of VLS...
With the advent of deep-submicron technologies, leakage power dissipation is a major concern for sca...
nevertheless the leakage currents are leftover as an adverse effect. The problem has taken a serious...