Towards on-chip fault-tolerant communication

Abstract — As CMOS technology scales down into the deepsubmicron (DSM) domain, devices and interconnects are subject to new types of malfunctions and failures that are harder to predict and avoid with the current system-on-chip (SoC) design methodologies. Relaxing the requirement of 100 % correctness in operation drastically reduces the costs of design but, at the same time, requires SoCs be designed with some degree of system-level faulttolerance. In this paper we introduce a high-level model of DSM failure patterns and propose a new communication paradigm for SoCs, namely stochastic communication. Specifically, for a generic tile-based architecture, we propose a randomized algorithm which not only separates computation from communication, but also provides the required fault-tolerance to on-chip failures. This new technique is easy and cheap to implement in SoCs that integrate a large number of communicating IP cores. I