A Physically Oriented Model to Quantify the Noise-on-Delay Effect

Abstract. The increase in dynamic on-chip noise has led to severe signal integrity problems in modern chip design. With respect to capacitive cross-talk there are two major fault mechanisms: false switching and the noise-on-delay effect. In a new approach an analytical, physically motivated model is proposed which quantifies the noise-on-delay effect aiming at quick timing verification. The accuracy of the model is validated in a comparison with the results of a circuit simulator. Moreover, its application in a standard design flow is demonstrated. As the model is based on physical circuit parameters it is also well suited for what-if analysis.