Test Compaction for At-Speed Testing of Scan Circuits Based on Non-Scan Test Sequences and Removal of Transfer Sequences

Abstract—We propose a procedure for generating compact test sets with enhanced at-speed testing capabilities for scan circuits. Compaction refers here to a reduction in the test application time, while at-speed testing refers to the application of primary input sequences that contribute to the detection of delay defects. The proposed procedure generates an initial test set that has a low test application time and consists of long sequences of primary input vectors applied consecutively. To construct this test set, the proposed procedure transforms a test sequence H for the nonscan circuit into a scan-based test by selecting an appropriate scan-in state and removing primary input vectors from H if they do not contribute to the fault coverage. If H contains long transfer sequences, several scan-based tests with long primary input sequences may be obtained by replacing transfer sequences in H with scan operations. This helps reduce the test application time further. We demonstrate through experimental results the advantages of this approach over earlier ones as a method for generating test sets with minimal test application time and long primary input sequences. Index Terms—At-speed testing, scan-based circuits, test application time, test compaction. I