Add to ORKGA virtual duplex system can be used to increase safety without the use of structural redundancy on a single machine. If a program P is calculating a given function f, then a virtual duplex system con-tains two variants Pa and Pb of P which are calculating the diverse functions fa and fb, respectively. If no error occurs in the process of designing and executing Pa and Pb then f = fa = fb holds. For a given input i the VDS calculates and compares the values fa(i) and fb(i). The presence of an error can be detected if fa(i) <> fb(i). This paper outlines the design of a Pentium II based system which aims at the automatic generation of VDS's with a high detection probability for hardware faults. 1
In this paper, a methodology for generating VHDL de-scriptions of hardware checkers is presented. It...
Duplex architectures naturally provide high safety because errors are easily detected by comparing t...
[[abstract]]In this paper, we propose a method of using an FPGA-based emulation system for fault gra...
Virtual Duplex Systems provide detection of and recovery from transient as well as most permanent ha...
Hardware duplication techniques are widely used for concurrent error detection in dependable systems...
Abstract: Virtual duplex systems have emerged as an alternative to traditional duplex systems, tradi...
The state of the art in integrated circuit design is the use of special hardware description languag...
ISBN: 0306435314Proposes an extended duplex architecture allowing one to reduce the general costs of...
Reconfigurable computing is an old concept that during the past couple of decades has become increas...
Concurrent error detection (CED) techniques (based on hardware duplication, parity codes, etc.) are ...
.This paper introduces a new approach in the debugging of hardware designs. The design is given as a...
We develop a microprocessor design that tolerates hard faults, including fabrication defects and in-...
Test generation is an important part of a circuit as the test vectors are used during the design, ma...
Modern processors continue to aggressively scale down the feature size and reduce voltage levels to ...
[[abstract]]In this paper, we introduce a method that uses the held programmable gate array (FPGA)-b...
In this paper, a methodology for generating VHDL de-scriptions of hardware checkers is presented. It...
Duplex architectures naturally provide high safety because errors are easily detected by comparing t...
[[abstract]]In this paper, we propose a method of using an FPGA-based emulation system for fault gra...
Virtual Duplex Systems provide detection of and recovery from transient as well as most permanent ha...
Hardware duplication techniques are widely used for concurrent error detection in dependable systems...
Abstract: Virtual duplex systems have emerged as an alternative to traditional duplex systems, tradi...
The state of the art in integrated circuit design is the use of special hardware description languag...
ISBN: 0306435314Proposes an extended duplex architecture allowing one to reduce the general costs of...
Reconfigurable computing is an old concept that during the past couple of decades has become increas...
Concurrent error detection (CED) techniques (based on hardware duplication, parity codes, etc.) are ...
.This paper introduces a new approach in the debugging of hardware designs. The design is given as a...
We develop a microprocessor design that tolerates hard faults, including fabrication defects and in-...
Test generation is an important part of a circuit as the test vectors are used during the design, ma...
Modern processors continue to aggressively scale down the feature size and reduce voltage levels to ...
[[abstract]]In this paper, we introduce a method that uses the held programmable gate array (FPGA)-b...
In this paper, a methodology for generating VHDL de-scriptions of hardware checkers is presented. It...
Duplex architectures naturally provide high safety because errors are easily detected by comparing t...
[[abstract]]In this paper, we propose a method of using an FPGA-based emulation system for fault gra...