Presenter: Graduate Student M.Sc. program presenter in platform presentation. A Clustered SMT Architecture for Scalable Embedded Processors ABSTRACT

Power consumption and wire delays are two limiting factors in designing embedded systems with a centralized architecture. Traditionally, the majority of embedded systems have used either VLIW or superscalar architectures. Recently, Simultaneous Multithreaded (SMT) architecture processors have appeared commercially such as the Intel Pentium 4 and the IBM Power 5. SMT architectures differ from superscalar processors in allowing multiple threads to execute concurrently and share resources. This allows better utilization of processor resources and potentially better performance. Recently, several studies have been exploring SMT architectures for embedded systems. Clustering is a technique by which resources are partitioned between threads to reduce wire delays, complexity, and power consumption, as well as enhance scalability. These advantages make clustering suitable for embedded systems, which favor cost and power consumption over performance. In this work we study the different clustering options of an SMT processor favoring the reduction of power consumption and their effects on performance. We concentrate on how new processor features such as clustered SMT can be tailored to benefit embedded processors. CLUSTERED SMT EMBEDDED PROCESSORS Embedded processor architectures differ from general purpose processor architectures in thei