Nanoscale technology promises dramatic increases in device density, but reliability is decreased as a sideeffect. With bit-error rates projected to be as high as 10%, designing a usable nanoscale memory system poses a significant challenge. Storing defect information corresponding to every bit in the nanoscale device using a reliable storage bit is prohibitively costly. Using a Bloom filter to store a defect map provides better compression at the cost of a small false positive rate (usable memory mapped as defective). Using a list-based technique for storing defect maps performs well for correlated errors, but poorly for randomly distributed defects. In this paper, we propose an algorithm for partitioning correlated defects from random ones...
A content addressable memory (CAM) is an SRAM-based memory that can be accessed in parallel to searc...
In this paper, we develop a theoretical framework for the analysis and design of fault-tolerant memo...
Process parameter variations are expected to be significantly high in a sub-50-nm technology regime,...
Abstract — Nanoscale technology promises dramatically in-creased device density, but also decreased ...
Memory Built In Self Repair (BISR) is gaining importance since several years. Because defect densiti...
Abstract — This paper proposes a nanoscale content addressable memory (CAM) architecture. The type ...
This paper presents memory Built-In Self-Repair approaches allowing to achieve high yield for defect...
We have calculated the maximum useful bit density that may be achieved by the synergy of bad bit exc...
Emerging nanoelectronic memories such as Resistive Random Access Memories (RRAMs) are possible candi...
This work presents a statistical analysis of nanocrystal (NC) memory reliability. Characterization o...
Newer defects in memories arising from shrinking manufacturing technologies demand improved memory t...
Memory Built In Self Repair (BISR) is gaining importance since several years. New fault tolerance ap...
In future nanotechnologies failure densities are predicted to be several orders of magnitude higher ...
We introduce a nanowire-based, sublithographic memory ar-chitecture tolerant to transient faults. Bo...
Emerging nano-scaled electronics such as silicon nanowires (NW) and quantum-dot cellular automata (Q...
A content addressable memory (CAM) is an SRAM-based memory that can be accessed in parallel to searc...
In this paper, we develop a theoretical framework for the analysis and design of fault-tolerant memo...
Process parameter variations are expected to be significantly high in a sub-50-nm technology regime,...
Abstract — Nanoscale technology promises dramatically in-creased device density, but also decreased ...
Memory Built In Self Repair (BISR) is gaining importance since several years. Because defect densiti...
Abstract — This paper proposes a nanoscale content addressable memory (CAM) architecture. The type ...
This paper presents memory Built-In Self-Repair approaches allowing to achieve high yield for defect...
We have calculated the maximum useful bit density that may be achieved by the synergy of bad bit exc...
Emerging nanoelectronic memories such as Resistive Random Access Memories (RRAMs) are possible candi...
This work presents a statistical analysis of nanocrystal (NC) memory reliability. Characterization o...
Newer defects in memories arising from shrinking manufacturing technologies demand improved memory t...
Memory Built In Self Repair (BISR) is gaining importance since several years. New fault tolerance ap...
In future nanotechnologies failure densities are predicted to be several orders of magnitude higher ...
We introduce a nanowire-based, sublithographic memory ar-chitecture tolerant to transient faults. Bo...
Emerging nano-scaled electronics such as silicon nanowires (NW) and quantum-dot cellular automata (Q...
A content addressable memory (CAM) is an SRAM-based memory that can be accessed in parallel to searc...
In this paper, we develop a theoretical framework for the analysis and design of fault-tolerant memo...
Process parameter variations are expected to be significantly high in a sub-50-nm technology regime,...