Add to ORKGAll synthesis efforts targeting reconfigurable logic face the challenge of creating designs that comply with the resource and storage capacity of the target device. Hence, area cost estimation is of significant importance in all stages of the hardwar
We propose a hypergraph model and a new algorithm for hardware allocation. The use of a hypergraph m...
Synchronous dataflow graphs (SDFGs) are widely used to model streaming applications such as signal p...
Field-programmable gate arrays (FPGA) technology can offer significantly higher performance at much ...
In this paper, we propose algorithms for presynthesis estimation of hardware cost of a streaming acc...
In this paper, we describe a comprehensive high-level synthesis system for control-flow intensive as...
Early power estimation requires one to estimate the area (gate count) of a design from a high-level ...
In this paper a unified approach of lower bound functional area and cycle budget estimations is pres...
This paper addresses the problem of estimating lower bounds on the power consumption in scheduled da...
Parallel computing platforms provide good performance for streaming applications within a limited po...
An important task in the system level synthesis process is estimating design parameters such as area...
In this paper, we describe a comprehensive high-level synthe-sis system for control-flow intensive a...
This thesis introduces new concepts to perform area-power-delay trade-offs in a logic synthesis syst...
A design approach is proposed to automatically identify and exploit runtime reconfiguration opportun...
Lower bound estimations of resources at various stages of high-level synthesis are essential to guid...
A Unified Lower Bound Estimation Technique for High-Level Synthesis The importance of effective lowe...
We propose a hypergraph model and a new algorithm for hardware allocation. The use of a hypergraph m...
Synchronous dataflow graphs (SDFGs) are widely used to model streaming applications such as signal p...
Field-programmable gate arrays (FPGA) technology can offer significantly higher performance at much ...
In this paper, we propose algorithms for presynthesis estimation of hardware cost of a streaming acc...
In this paper, we describe a comprehensive high-level synthesis system for control-flow intensive as...
Early power estimation requires one to estimate the area (gate count) of a design from a high-level ...
In this paper a unified approach of lower bound functional area and cycle budget estimations is pres...
This paper addresses the problem of estimating lower bounds on the power consumption in scheduled da...
Parallel computing platforms provide good performance for streaming applications within a limited po...
An important task in the system level synthesis process is estimating design parameters such as area...
In this paper, we describe a comprehensive high-level synthe-sis system for control-flow intensive a...
This thesis introduces new concepts to perform area-power-delay trade-offs in a logic synthesis syst...
A design approach is proposed to automatically identify and exploit runtime reconfiguration opportun...
Lower bound estimations of resources at various stages of high-level synthesis are essential to guid...
A Unified Lower Bound Estimation Technique for High-Level Synthesis The importance of effective lowe...
We propose a hypergraph model and a new algorithm for hardware allocation. The use of a hypergraph m...
Synchronous dataflow graphs (SDFGs) are widely used to model streaming applications such as signal p...
Field-programmable gate arrays (FPGA) technology can offer significantly higher performance at much ...