AN ENERGY EFFICIENT TCAM ENHANCED CACHE ARCHITECTURE Approved as to style and content by:

Chair of Advisory Committee: Dr. Rabi N. Mahapatra Microprocessors are used in a variety of systems ranging from high-performance super computers running scientific applications to battery powered cell phones performing real-time tasks. Due to the large disparity between processor clock speed and main memory access time, most modern processors include several caches, which consume more than half of the total chip area and power budget. As the performance gap between processors and memory has increased, the trend has been to increase the size of the on-chip caches. However, increasing the cache size also increases its access time and energy consumptions. This growing power dissipation problem is making traditional cooling and packaging techniques less effective thus requiring cache designers to focus more on architectural level energy efficiency than performance alone. The goal of this thesis is to propose a new cache architecture and to evaluate its efficiency in terms of miss rate, system performance, energy consumption, and area overhead. The proposed architecture employs the use of a few Ternary-CAM (TCAM) cells in the tag array to enable dynamic compression of tag entries containing contiguou