Add to ORKGIn this paper we motivate the explicit validation of hold-time violations in silicon and propose a method for doing so. New holdtime failure model and test pattern generation methodologies are defined. We outline conditions under which these tests can be applied reliably. We present results of applying these test patterns on a microprocessor and discuss the implications of intermittent failures on the relevance of hazards during timing analysis
With continued CMOS scaling, future shipped hardware will be increasingly vulnerable to in-the-field...
IC technologies are approaching the ultimate limits of silicon in terms of channel width, power supp...
Transient faults became an increasing issue in the past few years as smaller geometries of newer, hi...
The semiconductor industry has widely accepted transition delay fault (TDF) and path delay fault (PD...
[[abstract]]Hold-time violation is a common cause of failure at scan chains. A robust new paradigm f...
International audienceFor safety or AVS applications purpose, it isimportant to validate and to moni...
IC technologies are approaching the ultimate limits of silicon in terms of channel width, power supp...
Critical real-time embedded systems feature complex safety-related, performance-demanding functional...
Time redundant execution of tasks and comparison of results is a well-known technique for detecting ...
Abstract—As silicon technology continues to scale down and validation expenses continue to increase,...
Existing approaches for modular manufacturing testing of core-based systems-on-a-chip (SOCs) do not ...
textThis work deals with the problem of parametric failures in Integrated Circuits (ICs), focussing...
The increasing device count and design complexity are posing significant challenges to post-silicon ...
This paper addresses the run-time diagnosis of delay faults in functional units of microprocessors. ...
In late-age silicon, soft errors become an issue even for low-margin products. Since classical harde...
With continued CMOS scaling, future shipped hardware will be increasingly vulnerable to in-the-field...
IC technologies are approaching the ultimate limits of silicon in terms of channel width, power supp...
Transient faults became an increasing issue in the past few years as smaller geometries of newer, hi...
The semiconductor industry has widely accepted transition delay fault (TDF) and path delay fault (PD...
[[abstract]]Hold-time violation is a common cause of failure at scan chains. A robust new paradigm f...
International audienceFor safety or AVS applications purpose, it isimportant to validate and to moni...
IC technologies are approaching the ultimate limits of silicon in terms of channel width, power supp...
Critical real-time embedded systems feature complex safety-related, performance-demanding functional...
Time redundant execution of tasks and comparison of results is a well-known technique for detecting ...
Abstract—As silicon technology continues to scale down and validation expenses continue to increase,...
Existing approaches for modular manufacturing testing of core-based systems-on-a-chip (SOCs) do not ...
textThis work deals with the problem of parametric failures in Integrated Circuits (ICs), focussing...
The increasing device count and design complexity are posing significant challenges to post-silicon ...
This paper addresses the run-time diagnosis of delay faults in functional units of microprocessors. ...
In late-age silicon, soft errors become an issue even for low-margin products. Since classical harde...
With continued CMOS scaling, future shipped hardware will be increasingly vulnerable to in-the-field...
IC technologies are approaching the ultimate limits of silicon in terms of channel width, power supp...
Transient faults became an increasing issue in the past few years as smaller geometries of newer, hi...