This paper presents the design and use of reconfigurable stream processors for the physical layer processing in wireless base-stations. Stream processors, traditionally used for high performance media processing, use clusters of functional units to provide support for hundreds of functional units in a programmable architecture. We provide hardware support for reconfiguration in stream processors, enabling them to be power-efficient by adapting to the compute requirements of the application. We demonstrate the real-time implementation of a 32-user wireless base-station, employing multiuser channel estimation, multiuser detection and Viterbi decoding physical layer algorithms, supporting a data rate of 128 Kbps/user. The reconfigurable stream...
Abstract—This paper proposes a low-power high-throughput digital signal processor (DSP) for baseband...
The world of wireless communications is under constant change. Radio standards evolve and new standa...
The advantages of power-aware processors are well known. This paper presents an innovative processor...
Tech ReportThis paper presents the design and use of reconfigurable stream processors for the physic...
Stream processors support hundreds of functional units in a programmable architecture by clustering ...
We focus on architectures for streaming DSP applications such as wireless baseband processing and im...
This thesis concludes work conducted on exploring the usage of parallel and reconfigurableprocessor ...
Masters ThesisThis thesis demonstrates designing efficient algorithms and architectures to meet the ...
Summarization: The advantages of power-aware processors are well known. This paper presents an innov...
This thesis demonstrates the use of designing efficient algorithms and architectures to meet the rea...
Journal PaperThis paper presents alogrithms and architecture designs that can meet real-time require...
Conference PaperThis paper presents a multiprocessor solution to meet real-time requirements of impl...
This presentation will focus on algorithms and reconfigurable tiled architectures for streaming DSP ...
This book focuses on domain-specific heterogeneous reconfigurable architectures, demonstrating for r...
This chapter addresses reconfigurable heterogenous and homogeneous multicore system-on-chip (SoC) pl...
Abstract—This paper proposes a low-power high-throughput digital signal processor (DSP) for baseband...
The world of wireless communications is under constant change. Radio standards evolve and new standa...
The advantages of power-aware processors are well known. This paper presents an innovative processor...
Tech ReportThis paper presents the design and use of reconfigurable stream processors for the physic...
Stream processors support hundreds of functional units in a programmable architecture by clustering ...
We focus on architectures for streaming DSP applications such as wireless baseband processing and im...
This thesis concludes work conducted on exploring the usage of parallel and reconfigurableprocessor ...
Masters ThesisThis thesis demonstrates designing efficient algorithms and architectures to meet the ...
Summarization: The advantages of power-aware processors are well known. This paper presents an innov...
This thesis demonstrates the use of designing efficient algorithms and architectures to meet the rea...
Journal PaperThis paper presents alogrithms and architecture designs that can meet real-time require...
Conference PaperThis paper presents a multiprocessor solution to meet real-time requirements of impl...
This presentation will focus on algorithms and reconfigurable tiled architectures for streaming DSP ...
This book focuses on domain-specific heterogeneous reconfigurable architectures, demonstrating for r...
This chapter addresses reconfigurable heterogenous and homogeneous multicore system-on-chip (SoC) pl...
Abstract—This paper proposes a low-power high-throughput digital signal processor (DSP) for baseband...
The world of wireless communications is under constant change. Radio standards evolve and new standa...
The advantages of power-aware processors are well known. This paper presents an innovative processor...