Add to ORKGThis paper presents an effective approach to formally verify SystemC designs. The approach translates SystemC models into a Petri-Net based representation. The Petri-net model is then used for model checking of properties expressed in a timed temporal logic. The approach is particularly suitable for, but not restricted to, models at a high level of abstraction, such as transaction-level. The efficiency of the approach is illustrated by experiments
AbstractIn this paper we present algorithms for model checking CTL over systems specified as Petri n...
To deal with the ever growing complexity of Systems-on-Chip, designers use models early in the desig...
ABSTRACT SystemC has emerged lately as a de facto, open, industry standard modeling language, enabli...
There is an important trend towards design processes based on the reuse of predesigned components. W...
Abstract—Model checking is a powerful technique for verifying systems and detecting errors at early ...
Embedded systems are used in a wide spectrum of applications ranging from home appliances and mobile...
In this paper we present a formal verification approach for abstract SystemC models. The approach al...
This paper describes the formal verification of the recently introduced Dual Transition Petri Net (D...
Today’s complex systems are modeled on a high level of abstraction. In this context, C/C++-based des...
Time Petri Net (TPN) models have been widely used to the specification and verification of real-time...
Symbolic model checking is a powerful technique for checking temporal logic properties over finite o...
A novel approach for formal verification of SystemC designs is presented which is based on static an...
Abstract: Model-Checking is a formal verified technique to check on whether a computing model, by se...
Embedded systems are used in a wide spectrum of applications ranging from home appliances and mobile...
There is a lack of new verification methods that overcome the limitations of traditional validation ...
AbstractIn this paper we present algorithms for model checking CTL over systems specified as Petri n...
To deal with the ever growing complexity of Systems-on-Chip, designers use models early in the desig...
ABSTRACT SystemC has emerged lately as a de facto, open, industry standard modeling language, enabli...
There is an important trend towards design processes based on the reuse of predesigned components. W...
Abstract—Model checking is a powerful technique for verifying systems and detecting errors at early ...
Embedded systems are used in a wide spectrum of applications ranging from home appliances and mobile...
In this paper we present a formal verification approach for abstract SystemC models. The approach al...
This paper describes the formal verification of the recently introduced Dual Transition Petri Net (D...
Today’s complex systems are modeled on a high level of abstraction. In this context, C/C++-based des...
Time Petri Net (TPN) models have been widely used to the specification and verification of real-time...
Symbolic model checking is a powerful technique for checking temporal logic properties over finite o...
A novel approach for formal verification of SystemC designs is presented which is based on static an...
Abstract: Model-Checking is a formal verified technique to check on whether a computing model, by se...
Embedded systems are used in a wide spectrum of applications ranging from home appliances and mobile...
There is a lack of new verification methods that overcome the limitations of traditional validation ...
AbstractIn this paper we present algorithms for model checking CTL over systems specified as Petri n...
To deal with the ever growing complexity of Systems-on-Chip, designers use models early in the desig...
ABSTRACT SystemC has emerged lately as a de facto, open, industry standard modeling language, enabli...