The Routability of Multiprocessor Network Topologies in

A fundamental difference between ASICs and FPGAs is that wires in ASICs are designed such that it matches the requirements of a particular design. Wire parameters such as: length, width, layout and the number of wires are designed to meet the performance requirements. Oppositely, in an FPGA, the area is fixed and the routing resources exist whether or not they are used, so the goal changes to meeting the performance requirements within the limits of the available resources. In this paper, we investigate how this fundamental difference of resource usage affects the choice of network topology when building a Network-on-Chip for an FPGA. By exploring the routability of different multiprocessor network topologies on a single FPGA, we show that the underlying FPGA routing architecture does not benefit a particular topology. We also derive a cost metric that help us estimate the impact of the topology selection beyond 32 processors following a standard design flow and targeting commercial FPGAs