Abstract CJTAG: Enhancement to IEEE 1149.1 uses concurrent test to reduce test times

PCBs continue to become more complex each year with higher ball count BGA devices, larger memories and larger FPGAs. IEEE Std. 1149.1 has been instrumental in meeting the challenge of testing complex digital assemblies and maintaining high fault coverage. The complexity, however, has also caused test times using IEEE 1149.1 to increase since it is a serial protocol. Modern PCBs can now take three to six minutes to test and configure. These long test times have a direct influence on the test cost of a product. This paper describes an enhancement to IEEE 1149.1, called Concurrent JTAG that can be designed into an IC, PCB or System to reduce test and configuration times. Case studies are provided with test time reduction results