Abstract Breaking Down Complexity for Reliable System-Level Timing Validation

Complex embedded systems consist of hardware and software components from different domains, such as control and signal processing, many of them supplied by different internal and external source (e. g. IP). The system architect faces the challenge to integrate, optimize and validate the resulting heterogeneous systems. The analysis of the whole system is currently limited to simulation or emulation, since formal validation is only available for some subproblems. While simulation still seems viable for the validation of the system function, it can not be reliably applied to the validation of non-functional system properties, in particular timing. In this paper, we propose a validation methodology which augments existing cosimulation-based design approaches with formal timing analysis capabilities. This methodology is based on the decomposition of the validation task into the analysis of individual processes and resources for which formal analysis techniques are known and on the composition of the obtained results in order to obtain systemlevel timing information. Furthermore, it is shown how the analyzability of system timing can be systematically improved by slightly changing the system implementation.