Power Aware Framework for Dense Matrix Operations in Multimedia Processors

In this paper we analyze 1 the use of Decision Tree Grafting, Blocking and Loop Unfolding to improve the performance of dense matrix computations on high performance multimedia processors. The analysis focuses on the practical aspects that can be observed when programming on present DSP processor with multilayered memory levels. The problem is studied on the Philips Nexperia processor. The experimental evaluation of the proposed approach results into better exploitation of functional units, memory hierarchy and highway usage of the target processor. The advantages of the proposed interactive code transformation approach are twofolds. First, effort in optimization is spent only when the program measurement (transformation cost) determines that the effort is necessary and potentially beneficial, and only on those portions of the program where the energy/cycle performance payoff appears to be high. Second, by concatenating subsequent energy/cycle profile-driven low level transformations for higher level manipulations, the system will provide the programmer with a powerful toolset. The approach is illustrated using functional unit usage within a VLIW architecture for low power, which improves energy dissipation up to 34 % and CPU performance up to 87 % for an idct example. 1