Design and Characterization of NULL Convention Arithmetic Logic Units

computer arithmetic, ALU In this paper a number of 4-bit, 8-operation arithmetic logic units (ALUs) are designed using the delayinsensitive NULL Convention Logic (NCL) paradigm, and are characterized in terms of speed and area. Both dualrail and quad-rail, pipelined and non-pipelined versions are developed, and the tradeoffs and design considerations for each are discussed. Comparing the various architectures shows that the fastest dual-rail and quad-rail ALUs achieve average speedups of 1.72 and 1.59, respectively, over their non-pipelined counterparts, while requiring 133 % and 119 % more area, respectively. Overall, the dual-rail designs are both faster and require less area than their respective quad-rail counterparts; however, the quad-rail versions are expected to consume less power. 1