Design Trade-offs of a 6T FinFET SRAM Cell in the Presence of Variations

As the impact of process variations become increasingly significant in ultra deep submicron technologies, FinFETs are becoming increasingly popular a contender for replacement of bulk FETs due to favorable device characteristics. This paper explores the impacts of random and systematic process variations on SRAM cell stability and timing. The largest contributors to these robustness and timing metrics are identified. Design tradeoffs are explored in optimizing the SRAM cell for increased stability and timing.