Add to ORKGThere are always risks of missing bugs in functional verification. Using a formal analysis engine with very high capacity, we are able to eliminate such risks by formally proving that it is safe not to run a given class of test cases. This risk elimination solution works well with all verification flows because it only requires the waveform of a transaction and some user interaction (indicating what will be well verified about this transaction) in addition to the Verilog RTL. If it finds any test case in the class that can show any surprise, it generates a Verilog testbench to use in a normal simulation/debugging environment. Author(s) Biography Dr. Li is a verification solution architect. He also provides consulting services. His experienc...
textThe growing complexity of VLSI and System-on-a-chip(SoC) designs has made their verification ex...
In this paper we explore the specification and verification of VLSI designs. The paper focuses on ab...
Verification is too often approached in an ad hoc fashion. Moore's Law demands a productivity revolu...
The high degree of miniaturization in the electronics industry has been, for several years, a driver...
The high degree of miniaturization in the electronics industry has been, for several years, a driver...
After a few decades of research and experimentation, register-transfer dialects of two standard lang...
Formal Verification: An Essential Toolkit for Modern VLSI Design presents practical approaches for d...
Our work addresses the challenge of scaling pre-silicon functional verification of hardware designs ...
Functional Verification or Logical Simulation is an important phase in Digital Design Flow. It is to...
Formal Verification: An Essential Toolkit for Modern VLSI Design presents practical approaches for d...
The paper presents a sequence of three projects on design and formal verification of pipelined and s...
As the world increasingly depends on complex systems to transfer messages, store our data, and contr...
The goal of System Level Formal Verification is to show system correctness notwithstanding uncontrol...
A central issue in program verification is the generation of verification conditions (VCs): proof ob...
The functional correctness of safety- and security-critical software is of utmost importance. Nowada...
textThe growing complexity of VLSI and System-on-a-chip(SoC) designs has made their verification ex...
In this paper we explore the specification and verification of VLSI designs. The paper focuses on ab...
Verification is too often approached in an ad hoc fashion. Moore's Law demands a productivity revolu...
The high degree of miniaturization in the electronics industry has been, for several years, a driver...
The high degree of miniaturization in the electronics industry has been, for several years, a driver...
After a few decades of research and experimentation, register-transfer dialects of two standard lang...
Formal Verification: An Essential Toolkit for Modern VLSI Design presents practical approaches for d...
Our work addresses the challenge of scaling pre-silicon functional verification of hardware designs ...
Functional Verification or Logical Simulation is an important phase in Digital Design Flow. It is to...
Formal Verification: An Essential Toolkit for Modern VLSI Design presents practical approaches for d...
The paper presents a sequence of three projects on design and formal verification of pipelined and s...
As the world increasingly depends on complex systems to transfer messages, store our data, and contr...
The goal of System Level Formal Verification is to show system correctness notwithstanding uncontrol...
A central issue in program verification is the generation of verification conditions (VCs): proof ob...
The functional correctness of safety- and security-critical software is of utmost importance. Nowada...
textThe growing complexity of VLSI and System-on-a-chip(SoC) designs has made their verification ex...
In this paper we explore the specification and verification of VLSI designs. The paper focuses on ab...
Verification is too often approached in an ad hoc fashion. Moore's Law demands a productivity revolu...