Preface Preface

This project was conducted as a part of three independent, but collaborative master’s thesis. The original idea for this work was conceived by Peter Østergaard Nielsen from Vitesse Semiconductor Corporation, Denmark. I would like to thank my colleagues Martin Hans and Michael Kristensen for inspiring cooperation. Further I would like to thank Alberto Nannarelli for valuable insights and the administrative staff of IMM for helping me speed up the project work. Jacob Gregers Hansen, Copenhagen 2004. Leakage due to scaling down CMOS device sizes will be the major power consumption source in cell based IC design in a few years. This work addresses the problem of this leakage, investigating the possibilities of utilizing alternative logic families instead of static CMOS for the creation of a low leakage cell library. For this purpose, MTCMOS, CPL and Domino logic are investigated for leakage characteristics and are found unusable for low leakage design. Using cell libraries of small logic cells for IC design is found to be the major reason for much of the leakage. Synthesizing without cell boundaries by building larger cells reduces the leakage problem greatly. A new synthesis flow and cell library is proposed