The power consumption of a sequential circuit can be reduced by decomposing it into subcircuits which can be turned off when inactive. Power can also be reduced by careful state encoding. Modeling a given circuit as a finite-state machine, we formulate its decomposition into submachines as an integer linear programming (ILP) problem, and automatically generate the ILP model with power minimization as the objective. A simple, but powerful state encoding method is used for the submachines to further reduce power consumption. We present experimental results which show that circuits designed by our approach consume 30 % to 90 % less power than conventional circuits. Categories and Subject Descriptors
135 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1998.In the first part of the work...
This paper presents a state assignment technique called priority encoding which uses multi-code assi...
Finite State Machines (FSMs) are widely used for analysis and synthesis of hardware designs. In part...
In this paper we discuss the application of circuit-based logical reasoning to simplify optimization...
We address the problem of optimizing logic-level sequential circuits for low power. We present a pow...
In this thesis, we address the problem of optimizing sequential logic circuits for low power. We pre...
The continuous scaling down of transistor feature size poses several challenges to integrated circui...
The continuous scaling down of transistor feature size poses several challenges to integrated circui...
Clock gating is one of useful techniques to reduce the dynamic power consumption of synchronous sequ...
This paper presents a state assignment technique called priority encoding, which uses multi-code ass...
Power consumption of synchronous sequential circuits can be reduced by careful encoding of the state...
Power consumption of synchronous sequential circuits can be reduced by careful encoding of the state...
Power consumption of synchronous sequential circuits can be reduced by careful encoding of the state...
Power consumption of synchronous sequential circuits can be reduced by careful encoding of the state...
135 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1998.In the first part of the work...
135 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1998.In the first part of the work...
This paper presents a state assignment technique called priority encoding which uses multi-code assi...
Finite State Machines (FSMs) are widely used for analysis and synthesis of hardware designs. In part...
In this paper we discuss the application of circuit-based logical reasoning to simplify optimization...
We address the problem of optimizing logic-level sequential circuits for low power. We present a pow...
In this thesis, we address the problem of optimizing sequential logic circuits for low power. We pre...
The continuous scaling down of transistor feature size poses several challenges to integrated circui...
The continuous scaling down of transistor feature size poses several challenges to integrated circui...
Clock gating is one of useful techniques to reduce the dynamic power consumption of synchronous sequ...
This paper presents a state assignment technique called priority encoding, which uses multi-code ass...
Power consumption of synchronous sequential circuits can be reduced by careful encoding of the state...
Power consumption of synchronous sequential circuits can be reduced by careful encoding of the state...
Power consumption of synchronous sequential circuits can be reduced by careful encoding of the state...
Power consumption of synchronous sequential circuits can be reduced by careful encoding of the state...
135 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1998.In the first part of the work...
135 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1998.In the first part of the work...
This paper presents a state assignment technique called priority encoding which uses multi-code assi...
Finite State Machines (FSMs) are widely used for analysis and synthesis of hardware designs. In part...
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