Challenges in Nanometre Digital Integrated Circuit Design

Technology trends, driven by the desire for higher transistor densities and faster devices, have led to transistor dimensions scaling into the nanometre regime. However, with this continued scaling, digital Integrated Circuits (ICs) have faced many challenges that include: increased leakage power dissipation, increased process variations of transistor parameters and increased sensitivity of ICs to ionizing radiation from terrestrial and cosmic sources. These challenges are having a significant effect on circuit performance and power, making it more difficult to design circuits that achieve a required specification. This thesis presents new techniques for addressing these challenges in digital circuits. First, a new Static Random Access Memory (SRAM) cell is presented that reduces gate leakage power in caches while maintaining low access latency and stability. The new cell design, compared to a conventional SRAM cell, has one additional transistor and exploits the strong bias towards logic-0 at the bit level exhibited by the memory value stream of ordinary programs. Then, techniques for reducing leakage power i