Yield- Performance Tradeoffs for VLSI Processors with Partially Good Two-Level On-Chip Caches

In this paper a yield model for single chip VLSI processors with two level on-chip caches is derived. Using this model and trace tiven simulations the distribution of the faulty cache blocks into the first and second level caches can be determined so as to achieve a significant yield enhancement with the minimum performance degradation. The area devoted to on-chip caches in the modern processors is already a large fraction of the chip area and is expected to be larger in the near future. The cache arrays are fabricated with the tightest feature and scaling rules available in a given technology which means that caches are more susceptible to faults [ 1, 21. From the above we conclude that a substantial portion of the manufacturing defects wil