Performance Evaluation of A Novel CMP Cache Structure for Hybrid

Abstract. The Chip Multiprocessor (CMP) architecture offers parallel multi-thread execution and fast retrieval of shared data that is cached on-chip. In order to obtain the best possible performance with the CMP architecture, the cache architecture must be optimised to reduce time lost during remote cache and off-chip memory accesses. Many researchers proposed CMP cache architectures to improve the system performance, but they have not considered parallel execution of mixed single-thread and multi-thread workloads. In this paper, we propose a hybrid workload-aware cache architecture SPS2, in which each processor has both private and shared L2 caches. We describe the corresponding SPS2 cache coherence protocol with state transition graph. Performance evaluation demonstrates that the proposed SPS2 cache structure has better performance than traditional private L2 and shared L2 when hybrid workloads are applied. Keywords: Chip Multiprocessor, Cache Coherence Protocol, Hybrid Workload-aware