Perceptron-Based Branch Prediction: Performance of Some Design Options

Exploiting the huge computing power of modern microprocessors requires fast, accurate branch predictors: as clock rates rise and pipeline lengths grow, so do branch misprediction penalties. These latencies currently represent one of the largest microarchitectural performance bottlenecks. The literature is rich with techniques that increase accuracy, reduce prediction latencies, or both. Nonetheless, even with seemingly high prediction accuracies, branch misprediction latencies still have significant, negative performance effects on codes that are not memory bound. Some of the most novel recent proposals are based on the perceptron, a simple neural network component. We study a set of perceptron-based predictors that improve prediction accuracies over the originally proposed perceptron predictor by 18.2 % to 69.7%, with a mean of 37.6%. On the basis of our accuracy findings, we explore performance for a set of new perceptron-based predictors, comparing them to traditional schemes and to the best perceptron-based predictors published up to 2003 (the time of this study). For an Alpha 21264-like architecture, the new predictors increase IPC by up to 14.14 % over the 21264, and up to 9.28 % over the original perceptron (with means of 5.9 % and 3.67%, respectively). For an extended 20-stage pipeline, our designs improve IPCs by up to 19.35 % over the original perceptron. Better designs have been published subsequent to this study, but we nonetheless present our designs and results for the benefit of other researchers and practitioners.