Add to ORKGIn the past, instruction fetch speeds have been improved by using cache schemes that capture the actual program flow. In this paper, we elaborate on the architecture and operation of an instruction cache named Variable-Sized Block Cache (VSBC) that also makes use of the dynamic behavior of a program. Current trace-based cache schemes usually have some instructions stored repeatedly; this redundancy is eliminated in VSBC. Our cache also allows storage of basic blocks of arbitrary sizes, in multiple-way cache structure. An overall comparison of trace miss rate and average trace length shows VSBC to be a better performing cache scheme than TC, using SPECint2000 integer benchmarks
Trace caches are used to help dynamic branch prediction make multiple predictions in a cycle by embe...
A dynamic optimizer is a software-based system that performs code modifications at runtime, and seve...
Future processors combining out-of-order execution with aggressive speculation techniques will need ...
In the past, instruction fetch speeds have been improved by using cache schemes that capture the act...
In the past, instruction fetch speeds have been improved by using cache schemes that capture the act...
The trace cache is a recently proposed solution to achieving high instruction fetch bandwidth by buf...
As the instruction issue width of superscalar proces-sors increases, instruction fetch bandwidth req...
To maximize the performance of a wide-issue superscalar processor, the fetch mechanism must be capab...
We explore the use of compiler optimizations, which optimize the layout of instructions in memory. T...
In order to meet the demands of wider issue processors, fetch mechanisms will need to fetch multiple...
In the past, instruction fetch speeds have been improved by using cache schemes that capture the act...
Trace cache, an instruction fetch technique that reduces taken branch penalties by storing and fetch...
As the issue width of superscalar processors is increased, instruction fetch bandwidth requirements ...
In this paper we address the important problem of instruc-tion fetch for future wide issue superscal...
The design of higher performance processors has been following two major trends: increasing the pipe...
Trace caches are used to help dynamic branch prediction make multiple predictions in a cycle by embe...
A dynamic optimizer is a software-based system that performs code modifications at runtime, and seve...
Future processors combining out-of-order execution with aggressive speculation techniques will need ...
In the past, instruction fetch speeds have been improved by using cache schemes that capture the act...
In the past, instruction fetch speeds have been improved by using cache schemes that capture the act...
The trace cache is a recently proposed solution to achieving high instruction fetch bandwidth by buf...
As the instruction issue width of superscalar proces-sors increases, instruction fetch bandwidth req...
To maximize the performance of a wide-issue superscalar processor, the fetch mechanism must be capab...
We explore the use of compiler optimizations, which optimize the layout of instructions in memory. T...
In order to meet the demands of wider issue processors, fetch mechanisms will need to fetch multiple...
In the past, instruction fetch speeds have been improved by using cache schemes that capture the act...
Trace cache, an instruction fetch technique that reduces taken branch penalties by storing and fetch...
As the issue width of superscalar processors is increased, instruction fetch bandwidth requirements ...
In this paper we address the important problem of instruc-tion fetch for future wide issue superscal...
The design of higher performance processors has been following two major trends: increasing the pipe...
Trace caches are used to help dynamic branch prediction make multiple predictions in a cycle by embe...
A dynamic optimizer is a software-based system that performs code modifications at runtime, and seve...
Future processors combining out-of-order execution with aggressive speculation techniques will need ...