One of the primary challenges in embedded system design is designing the memory hierarchy and restructuring the application to take advantage of it. This task is particularly important for embedded image and video processing applications that make heavy use of large multidimensional arrays of signals and nested loops. In this paper, we show that a simple reuse vector/matrix abstraction can provide compiler with useful information in a concise form. Using this information, compiler can either adapt application to an existing memory hierarchy or can come up with a memory hierarchy. Our initial results indicate that the compiler is very successful in both optimizing code for a given memory hierarchy and designing a hierarchy with reasonable pe...
In this paper, we present a novel linear time algorithm for data remapping that is (i) lightweight, ...
Portable or embedded systems allow complex applica-tions like multimedia today. These memory intensi...
The memory hierarchy is the main bottleneck in modern computer systems as the gap between the speed ...
Abstract—This paper presents a compiler strategy to optimize data accesses in regular array-intensiv...
The trend in high-performance microprocessor design is toward increasing computational power on the ...
The trend in high-performance microprocessor design is toward increasing computational power on the ...
A tremendous amount of compiler research effort over the past ten years has been devoted to compensa...
Abstract—Exploiting runtime memory access traces can be a complementary approach to compiler optimiz...
Programming languages that provide multidimensional arrays and a flat linear model of memory must im...
Modern microprocessor designs continue to obtain impressive performance gains through increasing clo...
The design of future high-performance embedded systems is hampered by two problems: First, the requi...
The memory subsystem has traditionally been a major bottleneck in the design of high performance pro...
Modern microprocessor designs continue to obtain impressive per-formance gains through increasing cl...
ABSTRACT This paper presents the first memory allocation scheme for embedded systems having scratch-...
This article presents a methodology for automatic memory hierarchy generation that exploits memory a...
In this paper, we present a novel linear time algorithm for data remapping that is (i) lightweight, ...
Portable or embedded systems allow complex applica-tions like multimedia today. These memory intensi...
The memory hierarchy is the main bottleneck in modern computer systems as the gap between the speed ...
Abstract—This paper presents a compiler strategy to optimize data accesses in regular array-intensiv...
The trend in high-performance microprocessor design is toward increasing computational power on the ...
The trend in high-performance microprocessor design is toward increasing computational power on the ...
A tremendous amount of compiler research effort over the past ten years has been devoted to compensa...
Abstract—Exploiting runtime memory access traces can be a complementary approach to compiler optimiz...
Programming languages that provide multidimensional arrays and a flat linear model of memory must im...
Modern microprocessor designs continue to obtain impressive performance gains through increasing clo...
The design of future high-performance embedded systems is hampered by two problems: First, the requi...
The memory subsystem has traditionally been a major bottleneck in the design of high performance pro...
Modern microprocessor designs continue to obtain impressive per-formance gains through increasing cl...
ABSTRACT This paper presents the first memory allocation scheme for embedded systems having scratch-...
This article presents a methodology for automatic memory hierarchy generation that exploits memory a...
In this paper, we present a novel linear time algorithm for data remapping that is (i) lightweight, ...
Portable or embedded systems allow complex applica-tions like multimedia today. These memory intensi...
The memory hierarchy is the main bottleneck in modern computer systems as the gap between the speed ...