1 The Case for Building High Performance Intermediate-Level Memory Systems

This paper presents the architecture of a high-performance intermediate-level memory subsystem. The memory subsystem is designed to narrow the growing gap between processors’ cycle time and the round-trip delay to main memory. The system is built from high-performance DRAM arrays and SRAM buffers, both integrated on the same IC. We call these parts Integrated Static and Dynamic Random Access Memory (ISDRAM). The ISDRAM system is configured as a very large cache and can be implemented either as an on-chip cache integrated with the CPU, or as a much larger external cache. We show that building very large caches can be an effective way to narrow the growing CPU-memory speed gap. Building a cache as a combination of DRAM and SRAM yields a system with a relatively low cost per bit while achieving performance that is close to that of a system with a very large cache made of (expensive) fast SRAM. We demonstrate that ISDRAM cache, containing SRAM buffers that are only 1/64th the size of DRAM, performs almost as well as a conventional SRAM cache of the same size. “Back of the envelope ” estimates show that the ISDRAM bit-density should be approximately 1/2 the bit-density of commercial DRAM part