Distributed-shared-memory support on the Simultaneous Optical Multiprocessor Exchange Bus

This paper examines the performance of distributed-shared-memory systems based on the Simultaneous Optical Multiprocessor Exchange Bus (SOME-Bus) using queueing network models and develops theoretical results which predict processor utilization, message latency and other useful measures. It also presents simulation results which compare the performance of the SOME-Bus, the mesh and the torus using queueingnetwork models. The SOME-Bus is a low-latency, high-bandwidth, fiber-optic interconnection network which directly links arbitrary pairs of processor nodes without contention, and can efficiently interconnect over one hundred nodes. It contains a dedicated channel for the data output of each node, eliminating the need for global arbitration and providing bandwidth that scales directly with the number of nodes in the system. Each of N nodes has an array of receivers, with one receiver dedicated to each node output channel. No node is ever blocked from transmitting by another transmitter or due to contention for shared switching logic. The entire N-receiver array can be integrated on a single chip at a comparatively minor cost resulting in o(N) complexity. The SOME-Bus has much more functionality than a crossbar by supporting multiple simultaneous broadcasts of messages allowing cache consistency protocols to complete much faster. This paper demonstrates that, compared to the other networks considered here, the SOME-bus is the interconnection network whose performance is least affected by large message communication times. Processor utilization remains practically unaffected while it drops quite dramatically in the other architectures