Integrated Retiming and Simultaneous Vdd/Vth Scaling For Total Power Minimization ∗

The integration of retiming and simultaneous supply/threshold voltage scaling has a potential to enable more rigorous total power reduction. However, such integration is a highly complex task due to its enormous solution space. This paper presents the first algorithm that performs retiming and simultaneous supply/threshold voltage scaling. In our three-step approach, low power retiming is first performed to reduce the clock period while taking the FF delay/power into consideration. Next, the subsequent voltage scaling makes the best possible supply/threshold voltage assignment under the given clock period constraint set by the retiming. Finally, a post-process further refines the voltage scaling solution by exploiting the remaining timing slack in the circuit. Related experiments show that our min-FF retiming plus simultaneous Vdd/Vth scaling approach reduces the total power consumption by 34 % on average compared to the existing max-FF retiming plus Vdd Scaling approach