The Design and Implementation of the DVS Based Dynamic Compiler for Power Reduction *

Abstract. Recent years, as the wide deployment of embedded and mobile devices, reducing the power consumption in order to extend the battery life become a major factor that a designer must consider when designing a new architecture. DVS is regarded as one of the most effective power reduction techniques. This paper focus on run-time compiler driven DVS for power reduction, especially two key design issues include DVS analysis model and DVS decision algorithm. Based on the design framework presented in this work, we also implement a run-time DVS compiler which is fine-grained, adaptive to the program’s running environment without changing its behavior. The obtained system is deployed in a real hardware platform. Experimental results, based on some benchmarks, shows that with average 5 % performance loss, the benchmarks benefit with 26 % energy savings and the energy delay product (EDP) improvement is 22%.