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ARM®’s success to date has been largely due to its remarkable performance/power (MIPS/Watt) rating, and this will likely continue to be its most critical benchmark for future applications. This paper considers how attention to interdependent detail in cache controller design, conditionally executable instructions, intelligent voltage management, and interrupt control hardware contribute to the ARM architecture’s high performance and low power operation. Level 1 Cache Controller Design As CPU clock rates go higher and higher, Level 1 caches, which are implemented as part of the processor core, are a requirement when high performance, measured in terms of clocks per instruction (CPI) must be maintained, even when frequent access must be made to SDRAM or Flash memory external to the core. A cache, as illustrated in Figure 1 below, is a subsystem that includes two kinds of RAM and some logic that forms the cache controller. The cache is interposed between the CPU and slow system memory. The purpose of a cache is to make the slow memory system look like a fast memory system. The data RAM size is measured in bytes, but internally, it is organized as lines of memory. A lin