Scaling Instruction Window

Contemporary superscalar processors employ large instruction window to tolerate long latency (mainly second-level cache misses) and explore more instruction level parallelism (ILP); on the one hand, a larger instruction window can buffer larger number of instructions and find more independent instructions to execute, on the other hand, simply scaling instruction window as a unified and single unit complicates the wakeup/select logic and makes implementation much harder, besides, to execute more instructions in parallel needs more resources like register file, store buffer, reorder buffer, scheduler window, etc. More importantly, complicated wakeup/select and bypass logic from instruction window will increase processor cycle time in the front end, however current technology shows that clock speed is becoming faster and faster, so there will be an obvious trade off in the area of clock speed between the front end and the back end; also complicated logic and duplicate structure make energy and area consumption high. In order to solve the problems listed above, many papers have been published so far, and they mainly focused on the following few points: 1) instead of using a single unified large instruction window, a second level window is added to distinguish long and short latency instructions, and separate them for further operations; 2) aggressive resource reclamation mechanisms to release resource (registers, scheduler, ROB entries); 3) decoupling the back end from the front end to make the whole pipeline run at different cycle speed in different modes, 4) other issues including area and energy saving. All of the approaches listed above are interde