Add to ORKGCurrent trends indicate that leakage energy consumption will be an important concern in upcoming process technologies. In this paper, we propose a compiler-based leakage energy optimization strategy for on-chip scratch-pad memories (SPMs). The idea is to divide SPM into banks and use compiler-guided data layout optimization and data migration to maximize SPM bank idleness, thereby increasing the chances of placing banks into low-power (low-leakage) state
Abstract—Memory accesses are a major cause of energy con-sumption for embedded systems and the stack...
Nowadays, many embedded processors include in their architecture on-chip static memories, so called ...
[Abstract] On-chip power consumption is one of the fundamental challenges of current technology scal...
In VLSI systems-on-chips (SoC), leakage is expected to override 50% of the total power consumption, ...
Partitioning a memory into multiple blocks that can be independently accessed is a widely used techn...
Partitioning a memory into multiple blocks that can be independently accessed is a widely used techn...
The design of future high-performance embedded systems is hampered by two problems: First, the requi...
In an effort to make processors more power efficient scratch pad memory (SPM) have been proposed ins...
In order to meet the requirements concerning both performance and energy consumption in embedded sy...
Abstract—This paper presents a compiler strategy to optimize data accesses in regular array-intensiv...
The 16th Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI 2010...
A dynamic scratch pad memory (SPM) management scheme for program stack data with the objective of pr...
Scratch-pad memories (SPM) are small on-chip mem-ory devices whose access is much faster and consume...
CASES 2010 : International Conference on Compilers, Architecture, and Synthesis for Embedded System...
In this paper, we propose a new methodology for optimal memory mapping of data and instructions to S...
Abstract—Memory accesses are a major cause of energy con-sumption for embedded systems and the stack...
Nowadays, many embedded processors include in their architecture on-chip static memories, so called ...
[Abstract] On-chip power consumption is one of the fundamental challenges of current technology scal...
In VLSI systems-on-chips (SoC), leakage is expected to override 50% of the total power consumption, ...
Partitioning a memory into multiple blocks that can be independently accessed is a widely used techn...
Partitioning a memory into multiple blocks that can be independently accessed is a widely used techn...
The design of future high-performance embedded systems is hampered by two problems: First, the requi...
In an effort to make processors more power efficient scratch pad memory (SPM) have been proposed ins...
In order to meet the requirements concerning both performance and energy consumption in embedded sy...
Abstract—This paper presents a compiler strategy to optimize data accesses in regular array-intensiv...
The 16th Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI 2010...
A dynamic scratch pad memory (SPM) management scheme for program stack data with the objective of pr...
Scratch-pad memories (SPM) are small on-chip mem-ory devices whose access is much faster and consume...
CASES 2010 : International Conference on Compilers, Architecture, and Synthesis for Embedded System...
In this paper, we propose a new methodology for optimal memory mapping of data and instructions to S...
Abstract—Memory accesses are a major cause of energy con-sumption for embedded systems and the stack...
Nowadays, many embedded processors include in their architecture on-chip static memories, so called ...
[Abstract] On-chip power consumption is one of the fundamental challenges of current technology scal...